1. Field of the Invention
The present invention relates to a semiconductor device having electrostatic discharge (ESD) protecting means, and more particularly, to a semiconductor device having electrostatic discharge protecting means applied to a CMOS circuit.
2. Description of the Related Art
A semiconductor element such as a transistor included in a semiconductor circuit constituting a semiconductor device is sometimes seriously damaged in an electrostatic discharge event. A main source of an electrostatic discharge exposed to the semiconductor circuit is a human body (“human body model”, abbreviated as HBM), and the discharge from the human body generates current with a peak of several amperes to the semiconductor circuit for about 100 nanoseconds.
The second source of the discharge is a discharge from a metal object (“machine model”, abbreviated as MM), and this source quite possibly induces a transient in which a rise time is significantly larger than that of the electrostatic discharge in the HBM.
The third source comes from “charge device model” (CDM). In this model, a semiconductor element and the like themselves, which are included in the semiconductor circuit, are charged. In order to protect the semiconductor device from the electrostatic discharge, the charged electricity, which causes the discharge, should be discharged to the ground.
As all the devices are obliged to reduce dimensions thereof owing to demands for a faster operation speed, a lower operation voltage, a larger packing density, and less cost, protection from electrostatic discharge phenomena in the semiconductor circuit has become more important.
A description will be made on a semiconductor device including conventional electrostatic discharge protecting means based on FIG. 6. FIG. 6 shows the semiconductor device including the conventional electrostatic discharge protecting means (for example, refer to JP 5-180899 A).
In FIG. 6, the most common protecting means employed in a semiconductor circuit of a metal-oxide semiconductor (MOS) is a parasitic bipolar transistor associated with an NMOS transistor 117 formed on a semiconductor substrate 110. A drain 112 of the NMOS transistor 117 is connected to an input/output terminal 120 connected to a semiconductor circuit 121 to be protected, which is included in the semiconductor device, and a source 113 and gate 111 thereof are grounded. A protection level or a breakdown threshold value can be set by changing the gate length of the NMOS transistor 117 from the drain 112 to the source 113 below the gate 111 of the NMOS transistor 117. Under a stress condition, the parasitic bipolar transistor of the NMOS transistor 117 provides a dominant current conduction path between the to-be-protected input/output terminal 120 and a ground line 118 (the ground). The parasitic bipolar transistor operates in a snapback region when the polarity of a ground stress event is positive, and operates in forward-bias condition of a diode when the polarity is negative. Specifically, as long as the snapback region and forward-bias characteristics of the parasitic bipolar transistor operate normally, such an electrostatic discharge stress applied to the input/output terminal 120 is discharged, and accordingly, the semiconductor circuit 121 does not break. Since normal operation of the parasitic bipolar transistor in the snapback region or forward-bias condition assures the discharge of an electrostatic discharge stress applied to the input/output terminal 120, no breakdown occurs in the semiconductor circuit 121.
A main breakdown mechanism observed in an NMOS protection device operating as the parasitic bipolar transistor under such a snapback condition is a start of a second breakdown. The second breakdown is a phenomenon which always induces thermal runaway in the device when decrease of an impact ionization current is cancelled by thermal generation of carriers. The second breakdown starts in the device under the stress as a result of self-heating. It is known that the peak temperature of the NMOS device at which the second breakdown takes place rises together with the level of stress current.
The brief description has been made above of technology about electrostatic discharge in the conventional model, and the electrostatic discharge phenomenon and the protection method for the semiconductor circuit are described, for example, in JP 5-180899 A and “IEC standard, IEC-61000-4-2”.
In recent years, a new electrostatic discharge model has attracted attention. This electrostatic discharge model is called “air discharge model”, and this breakdown model assumes an electrostatic breakdown caused by a direct discharge from a charged body to an IC package.
FIG. 7 shows a simplified view of an electrostatic discharge measurement equivalent circuit for the air discharge model. In FIG. 7, static electricity is charged from a power supply 100 through a resistor 103 to a capacitance 105 when a switch 101 is on and a switch 102 is off. By putting off the switch 101 and putting on the switch 102, the static electricity charged in the capacitance 105 is applied through a resistor 104 to a circuit board 106 implementing a semiconductor circuit therein. A measurement method of this model is described in “IEC standard, IEC-61000-4-2”.
FIG. 8 shows a standard of an air discharge model in the IEC. Demand for Level 4 electrostatic discharge tolerance from the market increases the importance of an electrostatic discharge protection element.
The above-described conventional semiconductor device has the following problems. The electrostatic discharge protection in the HMB model, the MM model, and the CDM model can be made by the methods disclosed in JP 5-180899 A and “IEC standard, IEC-61000-4-2”. Insufficiency of the methods against the air discharge model, however, makes it difficult to respond to the market demand for Level 4 strength.
Though increase in the area of an electrostatic discharge protection element can resolve the above-described problem, the larger electrostatic discharge protection element and the increase in the area of the chip result in the following problem.
Connection of passive elements such as a resistor, a coil, and a capacitance to the electrostatic discharge protection element can yield higher electrostatic discharge voltage though, resulting not only possible increase in the chip area but also decrease in the CR time constant, which degrade the performance of the semiconductor device.
Further, the electrostatic discharge stress in the air discharge model is applied not only to the input/output terminal but also directly to the semiconductor circuit 121 in the inside of the chip. At this time, a problem occurs that the conventional method can respond to the application of the electrostatic discharge stress to the input/output terminal, but not to the electrostatic discharge stress applied directly to the internal semiconductor circuit 121 of the chip.